1. Field of the Invention
The present invention relates to a signal generating apparatus, a filter apparatus, a signal generating method and a filtering method.
2. Description of the Related Art
In wireless communications, various types of data, such as animation image data, still image data and music data, is transmitted and received. In recent years, the amount of the various types of data described above has tended to increase as the precision has increased, and therefore, a higher communication speed (transmitting and receiving performance) has become required for wireless communication. In general, a wide range of frequency bands is required in order to achieve high-speed communication. For example, it is necessary for wireless communication apparatuses to use a frequency band of several hundreds of MHz to several GHz in order to achieve a communication speed of several hundreds of Mbps to several Gbps.
In addition, it is necessary for wireless communication apparatuses to carry out appropriate signal processes, such as amplification, frequency conversion, frequency selection and gain adjustment on wideband signals having such a wide range of frequency bands using a CMOS process. Meanwhile, together with the miniaturization of CMOS's, there are restrictions in terms of the design, such as inconsistency in the properties between elements and reduction in the power supply voltage, and therefore, it is becoming more difficult to implement high-performance circuits for handling a wide-range signal. In particular, high element precision is generally required in filter circuits for selecting a frequency, and therefore, designing methods based on a continuous time analog circuit in related art could arrive at a bottleneck in the design of wireless communication apparatuses.
In view of this situation, a charge domain filter circuit of which the frequency properties are reconfigurable has been proposed as a filter circuit (see 2006 IEEE International Solid-State Circuits Conference 26.6 “An 800 MHz to 5 GHz Software-Defined Radio Receiver in 90 nm CMOS”). Charge domain filter circuits are provided with a number of capacitors and a number of switches for allowing each capacitor and an input terminal to be electrically connected on the basis of a control signal so that different capacitors sample an input signal in sequence.
Accordingly, it is necessary for control signals supplied to the respective switches not to have on periods (signal level at a first level) overlap. These control signals can be generated by driving a number of shift registers, for example.
In addition, IEEE Journal of Solid-State Circuits, Vol. 36, No. 6, June 2001 “A 1.25 GHz 0.35 m Monolithic CMOS PLL Based on a Multiphase Ring Oscillator” describes a ring oscillator which allows a number of multiphase clock signals, each of which has a predetermined phase difference, to be generated.